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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-12543-2E
8-bit Proprietary Microcontrollers
CMOS
F2MC-8L MB89580B/580BW Series
MB89583B/585B/589B/P585B/P589B/ MB89583BW/585BW/P585BW
s DESCRIPTION
The MB89580B/BW series is a line of general-purpose, single-chip microcontrollers. In addition to a compact instruction set, these microcontrollers contain a variety of peripheral functions, such as PLL clock control, timers, a serial interface, a PWM timer, and the USB function. In particular, these microcontrollers contain one USB function channel to support both high and low speeds.
s FEATURES
* Package type 64-pin LQFP package (0.5 mm pitch) and 64-pin QFP package (0.65 mm pitch) * High-speed operations at low voltage Minimum execution time : 0.33 s (Automatically generates a 12 MHz main clock and a 48 MHz USB interface synchronization clock with an externally supplied 6 MHz clock and the internal PLL circuit.) * F2MC-8L CPU core Instruction set that is optimum to the controllers -Multiplication and division instructions -16-bit arithmetic operations -branch instructions by bit testing -bit manipulation instructions, etc.
(Continued)
s PACKAGE
64-pin plastic LQFP 64-pin plastic QFP
(FPT-64P-M03)
(FPT-64P-M09)
MB89580B/580BW series
(Continued) * PLL clock control The internal PLL clock circuit allows the use of low-speed clocks which are advantageous to noise characteristics. (6 MHz externally-supplied clock : Internal system clock oscillated at 12 MHz)
* Various timers 8-bit PWM timer (can be used as either 8-bit PWM timer x 2 channels or PPG timer x 1 channel) Internal 21-bit timebase timer * Internal USB transceiver circuit (Compatible with high and low speeds) * USB function Compliant to USB Protocol Revision 1.0 Support for both low and full speeds (selectable) Allows four endpoints to be specified at maximum. Types of transfer supported : control/interrupt/bulk/isochronous Built-in DMAC (Maps the buffer for each endpoint on to the internal RAM to directly access the memory for function's send and receive data.) * UART/serial interface Built-in UART/SIO function (selectable by switching) * External interrupt External interrupt (level detection x 8 channels) Eight inputs are independent of one another and can also be used for resetting from low-power consumption mode (the L-level detection feature available) . * Low power consumption (standby mode supported) Stop mode (There is almost no current consumption since oscillation stops.) Sleep mode (This mode stops the running CPU.) * A maximum of 53 general-purpose I/O ports General-purpose I/O ports (CMOS) : 34 General-purpose output ports (CMOS) : 8 General-purpose I/O ports (Nch open drain) : 3 General-purpose input ports (CMOS 3.3 V input-compatible) : 8 * Parallel ports Also serve as eight of the general-purpose I/O ports (CMOS) Interrupt function available Allows asynchronous read and write by external signals * Power supply Supply voltage : 3.0 to 5.5 V
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MB89580B/580BW series
s PRODUCT LINEUP
Part number
MB89583B MB89585B
MB89P585B
MB89589B
MB89P589B
MB89583BW
MB89585BW
MB89P585BW
Parameter
ROM size RAM size Package Operation at USB reset Others
8 KB 512 B 1 KB
16 KB 18 KB QFP-64 (FPT-64P-M09)
8 KB 512 B
16 KB 1 KB
LQFP-64 (FPT-64P-M03)
LQFP-64 (FPT-64P-M03) Low-level output
High impedance state MASK product OTP/EVA product MASK product OTP/EVA product
MASK product
OTP/EVA product
CPU functions
Number of instructions Instruction bit length Instruction length Data bit length Minimum execution time Interrupt processing time General-purpose I/O ports General-purpose output ports General-purpose input ports
: 136 : 8 bits : 1 to 3 bytes : 1, 8, and 16 bits : 0. 33 s (6 MHz) : 3 s (6 MHz) (34 : CMOS, 3 : Nch open drain) (8 : CMOS) (8 : CMOS 3.3 V input)
Generalpurpose ports Parallel ports
Shares eight (P40 through P47) of the above general-purpose I/O ports. Allows asynchronous read and write by external signals. An interrupt function is available to set data. Can be set to full/low speed. Four endpoints at maximum Power supply mode : Can be set to own power supply/bus power supply mode. FIFO 8 bits x 8 built in Built-in DMAC (Can be set to DMA transfer to the internal RAM or to the external FIFO.)
Periph- USB eral function functions PWM timer 8-bit PWM timer operation x 2 channels (can also be used as a PPG x 1 channel timer) UART SIO Timebase timer Clock output Standby mode
Allows switching between UART (clock-synchronous/asynchronous data transfer allowed) and SIO (simple serial transfer) . 21-bit timebase timer Allows output of two main clock divisions Sleep mode and Stop mode
s PACKAGES AND CORRESPONDING PRODUCTS
Package FPT-64P-M03 FPT-64P-M09 : Available x x : Not available x x
MB89583B MB89585B
MB89P585B
MB89589B
MB89P589B
MB89583BW MB89585BW
MB89P585BW
x
x x x x
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MB89580B/580BW series
s DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the OTP product, verify its differences from the product that will actually be used.
2. Current Consumption
When operated at low speeds, a product mounted with either one-time PROM or EPROM consumes more current than a product mounted with a mask ROM. However, in sleep/stop mode the current consumption is the same. For detailed information on each package, see "s PACKAGE DIMENSIONS."
3. Differences Between the MB89580B series and the MB89580BW Series
MB89580B series : Remains in high impedance state until USB connection takes place. Before the USB connection, use one general-purpose port output to control pullup resistance connection of this port by software. MB89580BW : Outputs at low level until USB connection takes place.
* Example MB89580B product connection
3.3 V Host PC MB89580B series
General-purpose port 1.5 k D+ RPVP pin
D-
RPVM pin
* Example MB89580BW product connection
Host PC 3.3 V MB89580BW series
1.5 k
D+
RPVP pin
D-
RPVM pin
Note : Full speed is assumed in the above examples.
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MB89580B/580BW series
s PIN ASSIGNMENT
(TOP VIEW)
P43/D3/DO3 P42/D2/DO2 P41/D1/DO1 P40/D0/DO0 P67/DI7 P66/DI6 P65/DI5 P64/DI4 P63/DI3 P62/DI2 P61/DI1 P60/DI0 RPVM RPVP C VCC DO4/P44/UCK/D4 DO5/P45/UO/D5 DO6/P46/UI/PWM1/D6 DO7/P47/PWM2/D7 P30/INT0/CLK P31/INT1 P32/INT2 P33/INT3 P34/INT4 P35/INT5 P36/INT6/WEX P37/INT7/RDX P50/OBF/IBFX/W VSS P51/R P52/EFX 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17
P53/A0/FFX P54/CEX RST MOD0 MOD1 X0 X1 VSS P27 P26 P25 P24 P23 P22 P21 P20
(FPT-64P-M03) (FPT-64P-M09)
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MB89580B/580BW series
s PIN DESCRIPTION
Pin No. Pin name P44/UCK/D4/ DO4 P45/UO/D5/ DO5 P46/UI/ PWM1/D6/ DO6 P47/PWM2/ D7/DO7 Circuit type E Function General-purpose CMOS I/O pin UART/S10 clock I/O This pin also serves as a parallel interface/external FIFO data output pin. General-purpose CMOS I/O pin UART/S10 serial data output This pin also serves as a parallel interface/external FIFO data output pin. General-purpose CMOS I/O pin UART/S10 serial data input PWM timer This pin also serves as a parallel interface/external FIFO data output pin. General-purpose CMOS I/O pin PWM timer This pin also serves as a parallel interface/external FIFO data output pin. General-purpose CMOS I/O pin Clock output pin This pin also serves as an external interrupt input pin. The external interrupt input is a hysteresis input. (Level detection) General-purpose CMOS I/O pin This pin also serves as an external interrupt input pin. The external interrupt input is a hysteresis input. (Level detection) General-purpose CMOS I/O pin This pin also serves as an external interrupt input pin. The external interrupt input is a hysteresis input. (Level detection) General-purpose CMOS I/O pin This pin also serves as an external interrupt input pin. The external interrupt input is a hysteresis input. (Level detection) General-purpose CMOS I/O pin This pin also serves as an external interrupt input pin. The external interrupt input is a hysteresis input. (Level detection) General-purpose CMOS I/O pin This pin also serves as an external interrupt input pin. The external interrupt input is a hysteresis input. (Level detection) General-purpose CMOS I/O pin This pin also serves as an external interrupt input pin. The external interrupt input is a hysteresis input. (Level detection) This pin also serves as the parallel interface write strobe input pin. General-purpose CMOS I/O pin This pin also serves as an external interrupt input pin. The external interrupt input is a hysteresis input. (Level detection) This pin also serves as the parallel interface read strobe input pin. General-purpose CMOS I/O pin Interrupt output to the parallel interface host. This pin also serves the OUT FIFO data strobe pin.
1
2
B
3
E
4
B
5
P30/INT0/ CLK
E
6
P31/INT1
E
7
P32/INT2
E
8
P33/INT3
E
9
P34/INT4
E
10
P35/INT5
E
11
P36/INT6/ WEX
E
12
P37/INT7/ RDX
E
13
P50/OBF/ IBFX/W
B
(Continued)
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MB89580B/580BW series
Pin No. 14 15 16
Pin name VSS P51/R P52/EFX
Circuit type B K Power supply pin (GND)
Function
General-purpose CMOS I/O pin. This pin also serves the IN FIFO data strobe pin. General-purpose Nch open drain I/O pin. This pin also serves as the IN FIFO data enable input pin. General-purpose Nch open drain I/O pin. Parallel interface's data select input This pin also serves as the OUT FIFO data enable input pin. General-purpose Nch open drain I/O pin. This pin also serves as the parallel interface device select input pin. Reset pin. (Reset on the negative logic low level.) An operating mode designation pin. Connect directly to Vss. An operating mode designation pin. Connect directly to Vss. Pins for the crystal oscillator (6 MHz) Power supply pin (GND) General-purpose CMOS output pin General-purpose CMOS output pin General-purpose CMOS output pin General-purpose CMOS output pin General-purpose CMOS output pin General-purpose CMOS output pin General-purpose CMOS output pin General-purpose CMOS output pin General-purpose CMOS I/O pin General-purpose CMOS I/O pin General-purpose CMOS I/O pin General-purpose CMOS I/O pin General-purpose CMOS I/O pin General-purpose CMOS I/O pin General-purpose CMOS I/O pin General-purpose CMOS I/O pin General-purpose CMOS I/O pin General-purpose CMOS I/O pin General-purpose CMOS I/O pin General-purpose CMOS I/O pin
17
P53/A0/FFX
K
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
P54/CEX RST MOD0 MOD1 X0 X1 VSS P27 P26 P25 P24 P23 P22 P21 P20 P17 P16 P15 P14 P13 P12 P11 P10 P07 P06 P05 P04
K I F F A B B B B B B B B B B B B B B B B B B B B
(Continued)
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MB89580B/580BW series
(Continued)
Pin No. 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin name P03 P02 P01 P00 VCC C RPVP RPVM P60/DI0 P61/DI1 P62/DI2 P63/DI3 P64/DI4 P65/DI5 P66/DI6 P67/DI7 P40/D0/DO0 P41/D1/DO1 P42/D2/DO2 P43/D3/DO3 Circuit type B B B B Function General-purpose CMOS I/O pin General-purpose CMOS I/O pin General-purpose CMOS I/O pin General-purpose CMOS I/O pin Power supply pin Connect an external capacitor of 0.1 F. When using with 3.3 V power supply, connect this pin with the Vcc pin to set to 3.3 V input.
USBDRV USB route port + pin USBDRV USB router port - pin F F F F F F F F B B B B General-purpose CMOS input pin (3.3 V input) This pin also serves as an external FIFO data input pin. (LSB) General-purpose CMOS input pin (3.3 V input) This pin also serves as an external FIFO data input pin. General-purpose CMOS input pin (3.3 V input) This pin also serves as an external FIFO data input pin. General-purpose CMOS input pin (3.3 V input) This pin also serves as an external FIFO data input pin. General-purpose CMOS input pin (3.3 V input) This pin also serves as an external FIFO data input pin. General-purpose CMOS input pin (3.3 V input) This pin also serves as an external FIFO data input pin. General-purpose CMOS input pin (3.3 V input) This pin also serves as an external FIFO data input pin. General-purpose CMOS input pin (3.3 V input) This pin also serves as an external FIFO data input pin. (MSB) General-purpose CMOS I/O pin This pin serves as a parallel interface/external FIFO data output pin. General-purpose CMOS I/O pin This pin serves as a parallel interface/external FIFO data output pin. General-purpose CMOS I/O pin This pin serves as a parallel interface/external FIFO data output pin. General-purpose CMOS I/O pin This pin serves as a parallel interface/external FIFO data output pin.
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MB89580B/580BW series
s I/O CIRCUIT TYPE
Type
X1
Circuit
Remarks Oscillation feedback resistance Approx. 1 M
A
X0
CMOS I/O
R Pch Pch
Pullup control register
B
Nch Input
CMOS I/O
R Pch Pch Pullup control register
Hysteresis input
E
Nch Port input Resource input
CMOS input F
Input
Hysteresis I/O
R Pch
Pullup resistance
I
Nch
Input
(Continued)
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MB89580B/580BW series
(Continued) Type
Circuit USB I/O
D+ input D- input Operation input D- Full D+ output Full D- output Low D+ output Low D- output Direction
Remarks
D+
USBDRV
Speed
Nch open drain I/O
R Pch
Pullup control register
K
Nch Input
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MB89580B/580BW series
s HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than Vcc or lower than Vss is applied to input or output pins other than the medium- and high-voltage pins or if voltage higher than the rating is applied between Vcc and Vss. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also take care to prevent the analog input from exceeding the digital power supply (Vcc) when the power supply to the analog power system is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions and latchup leading to permanent damage to the pins. These unused pins should be connected to a pullup or pulldown resistance of at least 2 k between the pin and the power supply. Unused I/O pins should be placed in output state to leave it open or pins that are in input state should be handled the same as unused input pins.
3. Power Supply Voltage Fluctuations
Although Vcc power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that Vcc ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.
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MB89580B/580BW series
s ONE-TIME PROM AND EPROM MICROCONTROLLER PROGRAMMING SPECIFICATIONS
PROM mode is available on the MB89P585B/BW microcontrollers. The use of a dedicated adapter allows you to program the devices with a general-purpose ROM programmer. However, keep in mind that electronic signature mode is not available.
1. ROM programmer adapter and its compatible programmers
Package Compatible adapter Sun Hayato Co, Ltd. ROM2-64LQF-32DP-8LA Compatible programmers and models Ando Denki K. K. AF9708 (Version 1.40 or higher) AF9709 (Version 1.40 or higher) AF9723 (Version 1.50 or higher)
FTP-64P-M03 Inquiry: Sun Hayato Co., Ltd. Ando Denki K. K.
: TEL. 81-3-3986-0403 : TEL. 81-3-3733-1160
2. Memory map in PROM mode
Normal operating mode 0000H 0080H RAM 0480H Not available C000H I/O
(Corresponding addresses on the ROM programmer)
0000H
Program area (PROM)
Program area (PROM)
FFFFH
3FFFH
3. Programming the EPROM (Using the Ando Denki K.K. programmer)
(1) Set the EPROM programmer type code to 17209. (2) Load program data on to the EPROM programmer at 0000H to 3FFFH. (3) Program C000H to FFFFH with the EPROM programmer.
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MB89580B/580BW series
s BLOCK DIAGRAM
X0 X1
Main clock oscillator Reset output Clock control circuit
Power on reset circuit (watchdog timer)
RST
PLL circuit 21-bit timebase timer Internal bus 8-bit PWM timer CMOS I/O Port
P46/UI/PWM1/D6/DO6 P47/PWM2/D7/DO7
UART SIO USB DRV RPVP RPVM
P44/UCK/D4/DO4 P45/UO/D5/DO5
P40/D0/DO0 to P43/D3/DO3 USB Function circuit P00 to P07, P10 to P17 CMOS Out Port
P20 to P27
P51/R P50/OBF/IBFX/W P36/INT6/WEX P37/INT7/RDX P30/INT0/CLK P31/INT1 to P35/INT5 CMOS I/O Port Nch I/O Port
DMA
CMOS In Port
P60/DI0 to P67/DI7
Clock output External interrupt (level)
RAM 18 K / 1 K / 512 Byte
F2MC - 8L CPU
P52/EFX P53/FFX P54/CEX
ROM 8 K / 16 KByte
Other pins VSS VCC MOD0 MOD1 C
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MB89580B/580BW series
s CPU CORE
1. Memory Space
The MB89580B/BW microcontrollers offer a memory space of 64 Kbytes consisting of the I/O, RAM and ROM areas. The memory space contains areas that are used for specific purposes, such as a general-purpose register and a vector table. * I/O area (addresses : 0000H through 007FH) This area is assigned with the control and data registers, for example, of peripheral functions to be built in. The I/O area is as accessible as the memory since the area is assigned to a part of the memory space. Direct addressing also allows the area to be accessed faster. * RAM area As an internal data area, a static RAM is built in. The internal RAM capacity varies with the product type. The area 80H to FFH can be accessed at high speed with direct addressing. The area 100H to 1FFH can be used a general-purpose register area. (The usable area is limited depending on the product.) When reset, RAM data becomes undefined. * ROM area As an internal program area, a ROM is built in. The internal ROM capacity varies with the product type. The area FFCOH to FFFFH should be used for a vector table, for example. * Memory map
MB89585B MB89585BW MB89P585B MB89P585BW 0000H I/O 0080H RAM 512 B 0100H 0200H 0280H Generalpurpose register 0100H 0200H 0480H 4880H Not available Not available Not available E000H C000H C000H 0080H RAM 1 KB Generalpurpose register 0100H 0200H I/O 0080H RAM 18 KB Generalpurpose register 0000H I/O
MB89583B MB89583BW 0000H
MB89589B MB89P589B
ROM 8 KB
ROM* 16 KB
ROM* 16 KB
FFC0H FFFFH
FFC0H FFFFH Vector table (reset, interrupt and vector call instructions)
FFC0H FFFFH * : The area is EPROM on the MB89P585B, MB89P585BW, and MB89P589B microcontrollers.
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MB89580B/580BW series
2. Registers
The MB89580B/BW series has two types of registers; the registers dedicated to specific purposes in the CPU and the general-purpose registers. The dedicated registers are as follows: Program counter (PC) : A 16-bit register to indicate locations where instructions are stored. Accumulator (A) : A 16-bit register for temporary storage of operations. In the case of an 8-bit data processing instruction, the lower one byte is used. Temporary accumulator (T) : A 16-bit register which performs operations with the accumulator. In the case of an 8-bit data processing instruction, the lower one byte is used. Index register (IX) : A 16-bit register for index modification. Extra pointer (EP) : A 16-bit register to point to a memory address. Stack pointer (SP) : A 16-bit register to indicate a stack area. Program status (PS) : A 16-bit register to store a register pointer or a condition code.
16 bits PC A T IX EP SP RP PS CCR
: Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status
Initial value FFFDH Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate I-flag = 0, IL1, 0 = 11 Initial values for other bits are indeterminate.
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MB89580B/580BW series
The PS register can further be divided into the register bank pointer in the higher 8 bits (RP) and the condition code register in the lower 8 bits (CCR) . (See the diagram below.)
RP bit15 bit14 bit13 bit12 bit11 bit10 bit9 R4 R3 R2 R1 R0 - - H-Flag I-Flag IL 1,0 N-Flag Z-Flag V-Flag C-Flag bit8 - bit7 H bit6 I bit5 IL1 CCR bit4 IL0 bit3 N bit2 Z bit1 V bit0 C CCR initial value X011XXXXB
PS
X : Undefined
The RP points to the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule shown next. Rule for Conversion of Actual Addresses in the General-purpose Register Area
RP higher bits "0" Generated addresses "0" "0" "0" "0" "0" "0" A9 "1" A8 R4 A7 R3 A6 R2 A5 R1 A4 OP code in lower bits R0 A3 b2 A2 b1 A1 b0 A0
A15 A14 A13 A12 A11 A10
The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits that control CPU operations at the time of an interrupt. H flag : The flag is set to "1" when an arithmetic operation results in a carry from bit 3 to bit 4 or in a borrow from bit 4 to bit 3. The bit is cleared to "0" in other instances. The flag is for decimal adjustment instructions; do not use for other than additions and subtractions. : Interrupt is enabled when this flag is set to "1." Interrupt is disabled when this flag is set to "0." The flag is set to "0" when reset. : Indicates the level of the interrupt currently enabled. An interrupt is processed only if its level is higher than the value this bit indicates. IL1 0 0 1 1 IL0 0 1 0 1 Interrupt level 1 2 3 Lower = no interruption High-low Higher
I flag IL1, 0
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MB89580B/580BW series
N flag Z flag V flag C flag
: The flag is set to "1" when an arithmetic operation results in setting of the MSB to "1" or is cleared to "0" when the MSB is set to "1." : The flag is set to "1" when an arithmetic operation results in "0" or is set to "0" in other instances. : The flag is set to "1" when an arithmetic operation results in two's complement overflow or is cleared to "0" if no overflow occurs. : The flag is set to "1" when an arithmetic operation results in a carry from bit 7 or in a borrow to bit 7. The flag is cleared to "0" if neither of them occurs. In the case of a shift instruction, the flag is set to the shift-out value.
The following general-purpose registers are provided: General-purpose registers : 8-bit data storage registers The general-purpose registers are 8 bits in length and located in the register banks in the memory. One bank contains eight registers and the MB89580B/BW microcontrollers allow a total of 16 banks to be used at maximum. The bank currently in use is indicated by the register bank pointer (RP) .
Register Bank Configuration This address = 0100H + 8 x (RP)
R0 R1 R2 R3 R4 R5 R6 R7 16 banks
Memory area
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MB89580B/580BW series
s I/O MAP
Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H to 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH PURR0 PURR1 PURR2 PURR3 PURR4 PURR5 CTR1 CTR2 CTR3 CMR1 CMR2 PDR4 DDR4 PDR5 DDR5 PDR6 PDCR Port 4 data register Port 4 direction register Port 5 data register Port 5 direction register Port 6 data register Parallel port data control register Vacancy Port 0 pullup option setting register Port 1 pullup option setting register Port 2 pullup option setting register Port 3 pullup option setting register Port 4 pullup option setting register Port 5 pullup option setting register PWM control register 1 PWM control register 2 PWM control register 3 PWM compare register 1 PWM compare register 2 R/W R/W R/W R/W R/W R/W R/W R/W R/W W W 11111111 11111111 11111111 11111111 11111111 XXX 1 1 1 1 1 00000000 000X0000 X 0 0 0 XXXX XXXXXXXX XXXXXXXX PDR3 DDR3 Port 3 data register Port 3 direction register Vacancy Vacancy R/W R/W R/W R/W R/W R/W XXXXXXXX 00000000 XXX1 1 1XX XXXXXX 0 0 XXXXXXXX XXX0 0 0 0 0 SYCC STBC WDTC TBTC Standby control register Watchdog timer control register Timebase timer control register Vacancy R/W R/W XXXXXXXX 00000000 Register name PDR0 DDR0 PDR1 DDR1 PDR2 Register description Port 0 data register Port 0 direction register Port 1 data register Port 1 direction register Port 2 data register Vacancy Vacancy System clock control register R/W R/W R/W R/W XXX1 1X 0 0 0 0 0 1XXXX 0 XXXXXXX 0 0 XXX 0 0 0 Read/write R/W W R/W W R/W Initial value XXXXXXXX 00000000 XXXXXXXX 00000000 00000000
(Continued)
18
MB89580B/580BW series
Address 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H to 3BH 3CH 3DH 3EH to 3FH 40H 41H to 4EH 4FH 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH 60H 61H
Register name CKR SCS SMC1 SMC2 SSD SIDR/SODR SRC
Register description Clock output control register Serial clock switching register Vacancy Serial mode control register 1 Serial mode control register 2 Serial status and control register Serial input/serial output data register Serial rate control register Vacancy
Read/write R/W R/W R/W R/W R R/W R/W
Initial value XXXXXXX 0 XXXXXXX 0 00000000 00000000 0 0 0 0 1 XXX XXXXXXXX XXXXXXXX
EIE EIF
External interrupt control register External interrupt flag register Vacancy
R/W R/W
00000000 XXXXXXX 0
DMDR
USB power supply mode register Vacancy
R/W
XXXXXXX 0
DBARH UMDR DBAR TDCR0 TDCR11 TDCR12 TDCR21 TDCR22 TDCR3 UCTR USTR1 USTR2 UMSKR UFRMR1 UFRMR2 EPER EPBR0 EPBR11 EPBR12
DMA base address register H USB reset mode register DMA base address register Transfer data count register 0 Transfer data count register 11 Transfer data count register 12 Transfer data count register 21 Transfer data count register 22 Transfer data count register 3 USB control register USB status register 1 USB status register 2 USB interrupt mask register USB frame status register 1 USB frame status register 2 USB endpoint enable register Endpoint 0 setup register Endpoint setup register 11 Endpoint setup register 12
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R R R/W R/W R/W R/W
0 0 0 0 0 0 XX 1 0 0 0 XX 0 0 XXXXXXXX X0000000 00000000 XXXXXX 0 0 00000000 XXXXXX 0 0 X0000000 00000000 00000000 XXXXXX 0 0 00000000 XXXXXXXX XXXXXXXX XXXX 0 0 0 1 X0000000 0X000000 00000000
(Continued)
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MB89580B/580BW series
(Continued) Address Register name
62H 63H 64H 65H 66H to 7BH 7CH 7DH 7EH 7FH ILR1 ILR2 ILR3 EPBR21 EPBR22 EPBR31 EPBR32
Register description Endpoint setup register 21 Endpoint setup register 22 Endpoint setup register 31 Endpoint setup register 32 Vacancy Interrupt level setting register 1 Interrupt level setting register 2 level setting register 3 Vacancy
Read/write R/W R/W R/W R/W
Initial value 0X000000 00000000 XX 0 0 0 0 XX X0000000
W W W
11111111 11111111 11111111
* Information about read/write R/W : Read/write enabled, R : Read only, W : Write only * Information about initial values 0 : The initial value of this bit is "0." 1 : The initial bit of this bit is "1." X : The initial value of this bit is undefined. Note : Vacancies are not for use.
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MB89580B/580BW series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Value Min. VSS - 0.3 VSS - 0.3 VSS - 0.5 VSS - 0.3 -40 -55 Max. VSS + 6.0 VCC + 0.3 VSS + 4.0 VCC + 0.3 4 100 40 -15 -4 -50 -20 300 +85 +150 (VSS = 0 V) Unit V V V V mA mA mA mA mA mA mA mW C C Average value (operating current x operating rate) Average value (operating current x operating rate) Average value (operating current x operating rate) Average value (operating current x operating rate) Other than P60 to P67 P60 to P67 Remarks
Parameter Power supply voltage Input voltage Output voltage "L" level average output current "L" level total maximum output current "L" level total average output current "H" level maximum output current "H" level average output current "H" level total maximum output current "H" level total average output current Power consumption Operating temperature Storage temperature
Symbol VCC VI VO IOLAV IOL IOLAV IOH IOHAV IOH IOHAV PD TA Tstg
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
21
MB89580B/580BW series
2. Recommended Operating Conditions
Value Min. 3.0 -40 0.1 Typ. 16 Max. 5.5 +85 1.0
(VSS = 0 V) Unit V C F At Vcc = 5.0 V* When the USB function is in use Remarks
Parameter Power supply voltage Operating temperature Smoothing capacitor Series resistance
Symbol VCC TA CS RS
* : Use either a ceramic capacitor or a capacitor with similar frequency characteristics. The capacity of the smoothing capacitor for the Vcc pin should be greater than that of the Cs. When using with a supply voltage of 3.3 V, connect pin C with Vcc to input 3.3 V.
* C, RPVP and RPVM Pin Connection Diagram
RS RPVP RS RPVM
C CS
22
MB89580B/580BW series
5.5 5.0
Operating voltage VCC (V)
4.0
3.0
2.0
1.0
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0
CPU operating frequency (FCH MHz) (At instruction cycle 4/ FCH)
4.0
2.0
0.8
0.4
0.33
Minimum execution time (instruction cycle) (s) However, FCH = clock frequency (Fc) x 2
Figure 1 Operating voltage - operating frequency WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
23
MB89580B/580BW series
3. DC Characteristics
(VCC = 5.0 V, VSS = 0 V, TA = -40 C to +85 C) Pin name Condition Value Min. Typ. Max. Unit Remarks
Parameter
Symbol
VIH "H" level input voltage VIHS VIH1
P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P54, MOD0, MOD1 RST, INT0 to INT7, UCK, UI P60 to P67 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P54, MOD0, MOD1 RST, INT0 to INT7, UCK, UI P60 to P67 P52 to P54 P00 to P07, P10 to P17, P20 to P24, P30 to P37, P40 to P47, P50, P51 P00 to P07, P10 to P17, P20 to P24, P30 to P37, P40 to P47, P50 to P54, RST
0.7 VCC
VCC + 0.3
V

0.8 VCC VSS + 2.0

VCC + 0.3 VSS + 3.8
V V
VIL "L" level input voltage VILS VIL1 Open-drain output application voltage VD1
VSS - 0.3
0.3 VCC
V

VSS - 0.3 VSS - 0.5 VSS - 0.3

0.2 VCC VSS + 0.8 VCC + 0.3
V V V
"H" level output voltage
VOH
IOH = -2.0 mA
4.0
V
"L" level output voltage
VOL
IOL = 4.0 mA
0.4
V
(Continued)
24
MB89580B/580BW series
(Continued)
(VCC = 5.0 V, VSS = 0 V, TA = -40 C to +85 C) Symbol Pin name P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50, P51, P60 to P67 P52 to P54 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P54, RST Condition Value Min. Typ. Max. Unit Remarks
Parameter
Input leakage current (Hi-Z output leakage current) Open-drain output leakage current
ILI
0.0 < VI < VCC
-5
+5
A
When no pullup resistance is specified
ILIOD
0.0 < VI < VSS + 5.5
+5
A
Pullup resistance
RPULL
VI = 0.0 V
25
50
100
k
RST is excluded when pullup resistance available is specified.
ICC Power supply current ICCS1 ICCH Input capacitance CIN Other than Vcc and Vss VCC
FCH = 12.0 MHz VCC = 5.0 V tinst = 0.333 s FCH = 12.0 MHz VCC = 5.0 V tinst = 0.333 s TA = 25 C f = 1 MHz
25
38
MB89P585B/BW, MB89585B/BW, mA MB89583B/BW MB89P589B, MB89589B mA Sleep mode A pF Stop

20 5 10
30 20
25
MB89580B/580BW series
4. AC Characteristics
(1) Reset Timing (VCC = 5.0 V, VSS = 0 V, TA = -40 C to +85 C) Symbol tZLZH Condition Value Min. 16 tHCLY Max. Unit ns Remarks
Parameter RST "L" pulse width
Note : tHCYL is the internal main clock oscillating cycle (1/2 Fc) .
tZLZH
RST
0.2 VCC
0.2 VCC
(2) Power-on Reset and Power On Time Value Min. 0.066 4 Max. 50
(VSS = 0 V, TA = -40 C to +85 C) Condition Unit ms ns Due to repeated operations Remarks
Parameter Power supply rising time Power supply cutoff time
Symbol tR tOFF
Note : The power supply must be up within the selected oscillation stabilization time. When the supply voltage needs to be varied while operating, it is recommended to smoothly start up the voltage.
tR 3.5 V
tOFF
VCC
0.2 V 0.2 V 0.2 V
26
MB89580B/580BW series
(3) Clock Timing Value Min. Typ. 6 166.6 12 83.3 Max.
(VSS = 0 V, TA = -40 C to +85 C) Symbol FC tXCYL FCH tHCYL Pin name Condition X0, X1 X0, X1 Unit MHz ns MHz ns Twice the Fc tXCYL/2 Remarks
Parameter Clock frequency Clock cycle time Internal main clock frequency Internal clock cycle
* X0 and X1 Timing and Conditions
tXCYL
X0
0.2 VCC 0.2 VCC
* Clock Conditions
When a crystal resonator is used
X0
X1
C1
C2
(4) Instruction Cycle Parameter Instruction cycle (Min. execution time) Symbol tinst Value 4 / FCH, 8 / FCH, 16 / FCH, 64 / FCH Unit s
(VSS = 0 V, TA = -40 C to +85 C) Remarks When operating at FCH = 12 MHz tinst = 0.33 s (4 / FCH) 27
MB89580B/580BW series
(5) UART Serial I/O Timing
(VCC = 5.0 V, VSS = 0 V, TA = -40 C to +85 C) Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name UCK UCK, UO UI, UCK UCK, UI UCK UCK, UO UI, UCK UCK, UI External shift clock mode Internal shift clock mode Condition Value Min. 2 tinst -200 200 200 1 tinst 1 tinst 0 200 200 Max. 200 200 Unit s ns ns ns s s ns ns ns Remarks
Parameter Serial clock cycle time UCK UO Valid UI UCK UCK valid UI hold time Serial clock "H" pulse width Serial clock "L" pulse width UCK UO time Valid UI UCK UCK valid UI hold time
* : For information about tinst, see "Instruction Cycle." * Internal shift clock mode
tSCYC
UCK
2.4 V 0.8 V tSLOV 2.4 V 0.8 V tIVSH tSHIX 0.8 VCC 0.2 VCC 0.8 V
UO
UI
0.8 VCC 0.2 VCC
* External shift clock mode
tSLSH tSHSL 0.8 VCC 0.2 VCC tSLOV 2.4 V 0.8 V tIVSH tSHIX 0.8 VCC 0.2 VCC 0.2 VCC 0.8 VCC
UCK
UO
UI
0.8 VCC 0.2 VCC
28
MB89580B/580BW series
(6) Peripheral Input Timing
(VCC = 5.0 V, VSS = 0 V, TA = -40 C to +85 C) Pin name Condition INT0 to INT7 tIHIL1 2 tinst s Value Min. 2 tinst Max. Unit s Remarks
Parameter Peripheral input "H" pulse width 1 Peripheral input "L" pulse width 1
Symbol tILIH1
* : For information about tinst, see "Instruction Cycle."
tIHIL1
tILIH1 0.8 VCC 0.8 VCC
INT0 to INT7
0.2 VCC
0.2 VCC
29
MB89580B/580BW series
(7) Parallel Port Timing
(VCC = 5.0 V, VSS = 0 V, TA = -40 C to +85 C) Symbol tIHWL tCLWL tWHCH tWLWH tDVWH tWHDX tAVWH tWHAX tOHRL tCLRL tRHCH tRLRH tRLDV tRHDX tAVRL tRHAX Pin name IBFX WEX CEX WEX CEX WEX WEX D0 to D7 WEX D0 to D7 WEX A0 WEX A0 WEX OBF RDX CEX RDX CEX RDX RDX D0 to D7 RDX D0 to D7 RDX A0 RDX A0 RDX Condition Value Min. 1 / 2*tinst 0 0 40 10 10 10 10 1 / 2*tinst 0 0 40 0 10 10 Max. 15 Unit s ns ns ns ns ns ns ns s ns ns ns ns ns ns ns Remarks
Parameter IBFX WEX timing CEX WEX delay WEX CEX delay WEX pulse width Write data setup Write data hold Write address setup Write address hold OBF RDX timing CEX RDX delay RDX CEX delay RDX pulse width Read data delay Read data hold Read address setup Read address hold
30
MB89580B/580BW series
* Write Timing
IBFX
tIHWL
CEX
tCLWL tWHCH
WEX
tWLWH
D0 to D7
tDVWH
tWHDX
A0
tAVWH
tWHAX
* Read Timing
OBF
tOHRL
CEX
tCLRL tRHCH
RDX
tRLRH
D0 to D7
tRLDV
tRHDX
A0
tAVRL tRHAX
31
MB89580B/580BW series
(8) External FIFO Connection Timing
(VCC = 5.0 V, VSS = 0 V, TA = -40 C to +85 C, FC = 6 MHz) Condition Not including the initial resetting after reset Value Min. Max. 360 360 Unit Remarks Resetting before PKEND is not allowed.
Parameter
Symbol Pin name
FIFO empty resetting timing
tEFXH
EFX
0
ns
FIFO empty timing Read cycle time Read clock "H" pulse width Valid DI R setup time R valid DI hold time FIFO full reset timing FIFO full timing Write recycle time Write clock "H" pulse width Valid DO W setup time W valid DO hold time
tEFXL tRSCY tRHWD tDISP tDIHD tFFXH tFFXL tWSCY tWHWD tDOSP tDOHD
EFX, R R DI7 to DI0, R FFX FFX, W W DO7 to DO0, W
0 645 145 50 0 0 0 645 145 200 40
ns ns ns ns ns ns ns ns ns ns ns Resetting before PKEND is not allowed.
32
MB89580B/580BW series
* Read Data from External FIFO
PKEND
tEFXH
0.7 VCC
EFX (P52)
tRSYC 2.4 V tEFXL 2.4 V 0.8 V tDISP tDIHD
0.3 VCC
R (P51)
0.8 V tRHWD
DI7 to DI0
Invalid
2.0 V Valid 0.8 V
Invalid
Valid
Invalid
* Write Data to External FIFO
PKEND
tFFXH
FFX (P53)
tWSCY tFFXL 2.4 V 0.8 V tWHWD tDOSP 2.4 V
0.7 VCC 0.3 VCC
W (P50)
2.4 V
0.8 V tDOHD 2.4 V 0.8 V
DO7 to DO0
0.8 V
33
MB89580B/580BW series
s INSTRUCTIONS (136 INSTRUCTIONS)
Execution instructions can be divided into the following four groups: * Transfer * Arithmetic operation * Branch * Others Table 1 lists symbols used for notation of instructions. Table 1 Symbol dir off ext #vct #d8 #d16 dir: b rel @ A AH AL T TH TL IX EP PC SP PS dr CCR RP Ri x (x) (( x )) Instruction Symbols Meaning Direct address (8 bits) Offset (8 bits) Extended address (16 bits) Vector table number (3 bits) Immediate data (8 bits) Immediate data (16 bits) Bit direct address (8:3 bits) Branch relative address (8 bits) Register indirect (Example: @A, @IX, @EP) Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of accumulator A (8 bits) Lower 8 bits of accumulator A (8 bits) Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of temporary accumulator T (8 bits) Lower 8 bits of temporary accumulator T (8 bits) Index register IX (16 bits) Extra pointer EP (16 bits) Program counter PC (16 bits) Stack pointer SP (16 bits) Program status PS (16 bits) Accumulator A or index register IX (16 bits) Condition code register CCR (8 bits) Register bank pointer RP (5 bits) General-purpose register Ri (8 bits, i = 0 to 7) Indicates that the very x is the immediate data. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Indicates that the contents of x is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) The address indicated by the contents of x is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.)
Columns indicate the following: Mnemonic: Assembler notation of an instruction ~: The number of instructions #: The number of bytes Operation: Operation of an instruction TL, TH, AH: A content change when each of the TL, TH, and AH instructions is executed. Symbols in the column indicate the following: * "-" indicates no change. * dH is the 8 upper bits of operation description data. * AL and AH must become the contents of AL and AH prior to the instruction executed. * 00 becomes 00. N, Z, V, C: An instruction of which the corresponding flag will change. If + is written in this column, the relevant instruction will change its corresponding flag. OP code: Code of an instruction. If an instruction is more than one code, it is written according to the following rule: Example: 48 to 4F This indicates 48, 49, ... 4F. 34
MB89580B/580BW series
Table 2 Mnemonic MOV dir,A MOV @IX +off,A MOV ext,A MOV @EP ,A MOV Ri,A MOV A,#d8 MOV A,dir MOV A,@IX +off MOV A,ext MOV A,@A MOV A,@EP MOV A,Ri MOV dir,#d8 MOV @IX +off,#d8 MOV @EP ,#d8 MOV Ri,#d8 MOVW dir,A MOVW @IX +off,A MOVW ext,A MOVW @EP ,A MOVW EP ,A MOVW A,#d16 MOVW A,dir MOVW A,@IX +off MOVW A,ext MOVW A,@A MOVW A,@EP MOVW A,EP MOVW EP ,#d16 MOVW IX,A MOVW A,IX MOVW SP ,A MOVW A,SP MOV @A,T MOVW @A,T MOVW IX,#d16 MOVW A,PS MOVW PS,A MOVW SP ,#d16 SWAP SETB dir: b CLRB dir: b XCH A,T XCHW A,T XCHW A,EP XCHW A,IX XCHW A,SP MOVW A,PC Note ~ 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 5 4 2 3 4 5 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 # 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 3 1 1 3 2 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 Transfer Instructions (48 instructions) Operation (dir) (A) ( (IX) +off ) (A) (ext) (A) ( (EP) ) (A) (Ri) (A) (A) d8 (A) (dir) (A) ( (IX) +off) (A) (ext) (A) ( (A) ) (A) ( (EP) ) (A) (Ri) (dir) d8 ( (IX) +off ) d8 ( (EP) ) d8 (Ri) d8 (dir) (AH),(dir + 1) (AL) ( (IX) +off) (AH), ( (IX) +off + 1) (AL) (ext) (AH), (ext + 1) (AL) ( (EP) ) (AH),( (EP) + 1) (AL) (EP) (A) (A) d16 (AH) (dir), (AL) (dir + 1) (AH) ( (IX) +off), (AL) ( (IX) +off + 1) (AH) (ext), (AL) (ext + 1) (AH) ( (A) ), (AL) ( (A) ) + 1) (AH) ( (EP) ), (AL) ( (EP) + 1) (A) (EP) (EP) d16 (IX) (A) (A) (IX) (SP) (A) (A) (SP) ( (A) ) (T) ( (A) ) (TH),( (A) + 1) (TL) (IX) d16 (A) (PS) (PS) (A) (SP) d16 (AH) (AL) (dir): b 1 (dir): b 0 (AL) (TL) (A) (T) (A) (EP) (A) (IX) (A) (SP) (A) (PC) TL - - - - - AL AL AL AL AL AL AL - - - - - - - - - AL AL AL AL AL AL - - - - - - - - - - - - - - - AL AL - - - - TH - - - - - - - - - - - - - - - - - - - - - AH AH AH AH AH AH - - - - - - - - - - - - - - - - AH - - - - AH - - - - - - - - - - - - - - - - - - - - - dH dH dH dH dH dH dH - - dH - dH - - - dH - - AL - - - dH dH dH dH dH NZVC ---- ---- ---- ---- ---- ++-- ++-- ++-- ++-- ++-- ++-- ++-- ---- ---- ---- ---- ---- ---- ---- ---- ---- ++-- ++-- ++-- ++-- ++-- ++-- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ++++ ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- OP code 45 46 61 47 48 to 4F 04 05 06 60 92 07 08 to 0F 85 86 87 88 to 8F D5 D6 D4 D7 E3 E4 C5 C6 C4 93 C7 F3 E7 E2 F2 E1 F1 82 83 E6 70 71 E5 10 A8 to AF A0 to A7 42 43 F7 F6 F5 F0
During byte transfer to A, T A is restricted to low bytes. Operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (Reverse arrangement of F2MC-8 family)
35
MB89580B/580BW series
Table 3 Mnemonic ADDC A,Ri ADDC A,#d8 ADDC A,dir ADDC A,@IX +off ADDC A,@EP ADDCW A ADDC A SUBC A,Ri SUBC A,#d8 SUBC A,dir SUBC A,@IX +off SUBC A,@EP SUBCW A SUBC A INC Ri INCW EP INCW IX INCW A DEC Ri DECW EP DECW IX DECW A MULU A DIVU A ANDW A ORW A XORW A CMP A CMPW A RORC A ROLC A CMP A,#d8 CMP A,dir CMP A,@EP CMP A,@IX +off CMP A,Ri DAA DAS XOR A XOR A,#d8 XOR A,dir XOR A,@EP XOR A,@IX +off XOR A,Ri AND A AND A,#d8 AND A,dir ~ 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 2 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 # 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 Arithmetic Operation Instructions (62 instructions) Operation (A) (A) + (Ri) + C (A) (A) + d8 + C (A) (A) + (dir) + C (A) (A) + ( (IX) +off) + C (A) (A) + ( (EP) ) + C (A) (A) + (T) + C (AL) (AL) + (TL) + C (A) (A) - (Ri) - C (A) (A) - d8 - C (A) (A) - (dir) - C (A) (A) - ( (IX) +off) - C (A) (A) - ( (EP) ) - C (A) (T) - (A) - C (AL) (TL) - (AL) - C (Ri) (Ri) + 1 (EP) (EP) + 1 (IX) (IX) + 1 (A) (A) + 1 (Ri) (Ri) - 1 (EP) (EP) - 1 (IX) (IX) - 1 (A) (A) - 1 (A) (AL) x (TL) (A) (T) / (AL),MOD (T) (A) (A) (T) (A) (A) (T) (A) (A) (T) (TL) - (AL) (T) - (A) CA C A (A) - d8 (A) - (dir) (A) - ( (EP) ) (A) - ( (IX) +off) (A) - (Ri) Decimal adjust for addition Decimal adjust for subtraction (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) TL - - - - - - - - - - - - - - - - - - - - - - - dL - - - - - - - - - - - - - - - - - - - - - - - TH - - - - - - - - - - - - - - - - - - - - - - - 00 - - - - - - - - - - - - - - - - - - - - - - - AH - - - - - dH - - - - - - dH - - - - dH - - - dH dH 00 dH dH dH - - - - - - - - - - - - - - - - - - - - NZVC ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ +++- ---- ---- ++-- +++- ---- ---- ++-- ---- ---- ++R- ++R- ++R- ++++ ++++ ++-+ ++-+ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- OP code 28 to 2F 24 25 26 27 23 22 38 to 3F 34 35 36 37 33 32 C8 to CF C3 C2 C0 D8 to DF D3 D2 D0 01 11 63 73 53 12 13 03 02 14 15 17 16 18 to 1F 84 94 52 54 55 57 56 58 to 5F 62 64 65
(Continued)
36
MB89580B/580BW series
(Continued) Mnemonic
AND A,@EP AND A,@IX +off AND A,Ri OR A OR A,#d8 OR A,dir OR A,@EP OR A,@IX +off OR A,Ri CMP dir,#d8 CMP @EP ,#d8 CMP @IX +off,#d8 CMP Ri,#d8 INCW SP DECW SP
~ 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3
# 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1
Operation (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (dir) - d8 ( (EP) ) - d8 ( (IX) + off) - d8 (Ri) - d8 (SP) (SP) + 1 (SP) (SP) - 1 Table 4
TL - - - - - - - - - - - - - - -
TH - - - - - - - - - - - - - - -
AH - - - - - - - - - - - - - - -
NZVC ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++++ ++++ ++++ ++++ ---- ----
OP code 67 66 68 to 6F 72 74 75 77 76 78 to 7F 95 97 96 98 to 9F C1 D1
Branch Instructions (17 instructions) Operation TL - - - - - - - - - - - - - - - - - TH - - - - - - - - - - - - - - - - - AH - - - - - - - - - - - - - - dH - - NZVC ---- ---- ---- ---- ---- ---- ---- ---- -+-- -+-- ---- ---- ---- ---- ---- ---- Restore OP code FD FC F9 F8 FB FA FF FE B0 to B7 B8 to BF E0 21 E8 to EF 31 F4 20 30
Mnemonic BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BLT rel BGE rel BBC dir: b,rel BBS dir: b,rel JMP @A JMP ext CALLV #vct CALL ext XCHW A,PC RET RETI
~ 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6
# 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1
If Z = 1 then PC PC + rel If Z = 0 then PC PC + rel If C = 1 then PC PC + rel If C = 0 then PC PC + rel If N = 1 then PC PC + rel If N = 0 then PC PC + rel If V N = 1 then PC PC + rel If V N = 0 then PC PC + reI If (dir: b) = 0 then PC PC + rel If (dir: b) = 1 then PC PC + rel (PC) (A) (PC) ext Vector call Subroutine call (PC) (A),(A) (PC) + 1 Return from subrountine Return form interrupt Table 5
Other Instructions (9 instructions) Operation TL - - - - - - - - - TH - - - - - - - - - AH - dH - - - - - - - NZVC ---- ---- ---- ---- ---- ---R ---S ---- ---- OP code 40 50 41 51 00 81 91 80 90
Mnemonic PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI
~ 4 4 4 4 1 1 1 1 1
# 1 1 1 1 1 1 1 1 1
37
38
3 RETI PUSHW POPW MOV MOVW CLRI A A A,ext A,PS SETC SETI CLRB BBC INCW DECW JMP MOVW dir: 0 dir: 0,rel A A @A A,PC 4 5 6 7 8 9 A B C D E F CLRB BBC INCW DECW MOVW MOVW dir: 1 dir: 1,rel SP SP SP ,A A,SP SUBC A A A, T A A A XCH XOR AND OR
H
L
0
1
2
0
NOP
SWAP
RET
1
MULU
DIVU
A
A
JMP CALL PUSHW POPW MOV MOVW CLRC addr16 addr16 IX IX ext,A PS,A
2
ROLC
CMP
ADDC
s INSTRUCTION MAP
A
A
MOV MOV CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 2 dir: 2,rel IX IX IX,A A,IX
3
RORC
CMPW
A XOR AND OR DAA A,#d8 A,#d8 A,#d8 DAS
A
ADDCW SUBCW XCHW XORW ANDW ORW MOVW MOVW CLRB BBC INCW DECW MOVW MOVW A A A, T A A A @A,T A,@A dir: 3 dir: 3,rel EP EP EP ,A A,EP CLRB BBC MOVW MOVW MOVW XCHW dir: 4 dir: 4,rel A,ext ext,A A,#d16 A,PC
4
MOV CMP ADDC SUBC A,#d8 A,#d8 A,#d8 A,#d8
5
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,dir A,dir A,dir A,dir dir,A A,dir A,dir A,dir dir,#d8 dir,#d8 dir: 5 dir: 5,rel A,dir dir,A SP ,#d16 A,SP
MB89580B/580BW series
6
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,@IX +d A,@IX +d A,@IX +d A,@IX +d @IX +d,A A,@IX +d A,@IX +d A,@IX +d @IX +d,#d8 @IX +d,#d8 dir: 6 dir: 6,rel A,@IX +d @IX +d,A IX,#d16 A,IX
7
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,@EP A,@EP A,@EP A,@EP @EP ,A A,@EP A,@EP A,@EP @EP ,#d8 @EP ,#d8 dir: 7 dir: 7,rel A,@EP @EP ,A EP ,#d16 A,EP DEC R0 DEC R1 DEC R2 DEC R3 DEC R4 DEC R5 DEC R6 DEC R7 R7 R6 R5 R4 R3 R2 R1 R0 CALLV BNC #0 rel CALLV BC #1 CALLV BP #2 CALLV BN #3
8
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R0 A,R0 A,R0 A,R0 R0,A A,R0 A,R0 A,R0 R0,#d8 R0,#d8 dir: 0 dir: 0,rel
9
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R1 A,R1 A,R1 A,R1 R1,A A,R1 A,R1 A,R1 R1,#d8 R1,#d8 dir: 1 dir: 1,rel
rel
A
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R2 A,R2 A,R2 A,R2 R2,A A,R2 A,R2 A,R2 R2,#d8 R2,#d8 dir: 2 dir: 2,rel
rel
B
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R3 A,R3 A,R3 A,R3 R3,A A,R3 A,R3 A,R3 R3,#d8 R3,#d8 dir: 3 dir: 3,rel
rel CALLV BNZ #4 rel CALLV BZ #5
C
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R4 A,R4 A,R4 A,R4 R4,A A,R4 A,R4 A,R4 R4,#d8 R4,#d8 dir: 4 dir: 4,rel
D
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R5 A,R5 A,R5 A,R5 R5,A A,R5 A,R5 A,R5 R5,#d8 R5,#d8 dir: 5 dir: 5,rel
rel CALLV BGE #6 rel CALLV BLT #7
E
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R6 A,R6 A,R6 A,R6 R6,A A,R6 A,R6 A,R6 R6,#d8 R6,#d8 dir: 6 dir: 6,rel
F
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R7 A,R7 A,R7 A,R7 R7,A A,R7 A,R7 A,R7 R7,#d8 R7,#d8 dir: 7 dir: 7,rel
rel
MB89580B/580BW series
s ORDERING INFORMATION
Part number MB89589BPFM MB89P589BPFM MB89583BPFV MB89585BPFV MB89P585BPFV MB89583BWPFV MB89585BWPFV MB89P585BWPFV Package 64-pin plastic QFP (FPT-64P-M09) Remarks
64-pin plastic LQFP (FPT-64P-M03)
39
MB89580B/580BW series
s PACKAGE DIMENSION
64-pin plastic LQFP (FPT-64P-M03)
12.000.20(.472.008)SQ 10.000.10(.394.004)SQ
48 33
Note: Pins width and pins thickness include plating thickness.
49
32
0.08(.003)
Details of "A" part
INDEX
1.50 -0.10 .059 -.004
17
+0.20 +.008
(Mounting height)
64
"A" LEAD No.
1 16
0~8
+0.08 -0.03 +.003 -.001
0.500.08 (.020.003)
0.18 .007
0.08(.003)
M
0.1450.055 (.006.002) 0.500.20 (.020.008) 0.45/0.75 (.018/.030)
0.100.10 (.004.004) (Stand off) 0.25(.010)
C
1998 FUJITSU LIMITED F64009S-3C-6
Dimensions in mm (inches)
(Continued)
40
MB89580B/580BW series
(Continued) 64-pin plastic QFP (FPT-64P-M09)
14.000.20(.551.008)SQ
48
Note: Pins width and pins thickness include plating thickness.
12.000.10(.472.004)SQ
33
1.50 -0.10 .059 -.004
+0.20 +.008
(Mounting height)
49
32
9.75 (.384) REF 1 PIN INDEX
13.00 (.512) NOM
64
17
LEAD No.
1
16
Details of "A" part "A"
M
0.65(.0256)TYP
0.300.10 (.012.004)
0.13(.005)
0.127 -0.02 .005 -.001
+0.05 +.002
0.100.10 (STAND OFF) (.004.004)
0.10(.004) 0 10
0.500.20 (.020.008)
C
2000 FUJITSU LIMITED F64018S-1C-3
Dimensions in mm (inches)
41
MB89580B/580BW series
FUJITSU LIMITED
For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3386 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmap.com.sg/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The contents of this document may not be reproduced or copied without the permission of FUJITSU LIMITED. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
F0012 (c) FUJITSU LIMITED Printed in Japan

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